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74VCX162244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistor in Outputs
August 1997 Revised August 2001
74VCX162244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistor in Outputs
General Description
The VCX162244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The 74VCX162244 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX162244 is also designed with 26 series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74VCX162244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V-3.6V VCC supply operation s 3.6V tolerant inputs and outputs s 26 series resistors in outputs s tPD 3.3 ns max for 3.0V to 3.6V VCC 3.8 ns max for 2.3V to 2.7V VCC 7.6 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal s Static Drive (IOH/IOL)
12 mA @ 3.0V VCC 8 mA @ 2.3V VCC 3 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model > 200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74VCX162244GX (Note 2) 74VCX162244MTD (Note 3) Package Number BGA54A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS500040
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74VCX162244
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names OEn I0-I15 O0-O15 NC Description Output Enable Input (Active LOW) Inputs Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE4 4 OE2 NC VCC GND GND GND VCC NC OE3 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Pin Assignment for FBGA OE1 L L H Inputs OE2 L L H (Top Thru View) Inputs OE3 L L H Inputs OE4 L L H I12-I15 L H X I8-I11 L H X Outputs O8-O11 L H Z Outputs O12-O15 L H Z I4-I7 L H X Inputs I0-I3 L H X Outputs O0-O3 L H Z Outputs O4-O7 L H Z
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance
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74VCX162244
Functional Description
The 74VCX162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs.
Logic Diagram
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74VCX162244
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 5) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to VCC +0.5V -50 mA -50 mA +50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 6)
Power Supply Operating Data Retention Only Input Voltage Output Voltage (VO) Output in Active States Output in 3-State Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V 1.2V to 3.6V
-0.3V to +3.6V
0V to VCC 0.0V to 3.6V
12 mA 8 mA 3 mA -40C to +85C
DC Electrical Characteristics (2.7V < VCC 3.6V)
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -6 mA IOH = -8 mA IOH = -12 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 6 mA IOL = 8 mA IOL = 12 mA II IOZ IOFF ICC ICC Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input 0 VI 3.6V 0 VO 3.6V VI = VIH or VIL 0 (VI, VO) 3.6V VI = VCC or GND VCC (VI, VO) 3.6V (Note 7) VIH = VCC -0.6V
Note 7: Outputs disabled or 3-STATE only.
Conditions
VCC (V) 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 3.0 2.7-3.6 2.7 3.0 3.0 2.7-3.6 2.7-3.6 0 2.7-3.6 2.7-3.6 2.7-3.6
Min 2.0
Max
Units V
0.8 VCC - 0.2 2.2 2.4 2.2 0.2 0.4 0.55 0.8 5.0 10 10 20 20 750
V V V V V V V V V A A A A A A
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74VCX162244
DC Electrical Characteristics (2.3V V CC 2.7V)
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -4 mA IOH = -6 mA IOH = -8 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 6 mA IOL = 8 mA II IOZ IOFF ICC Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current 0 VI 3.6V 0 VO 3.6V VI = V IH or VIL 0 (VI, VO) 3.6V VI = V CC or GND VCC (VI, VO) 3.6V (Note 8)
Note 8: Outputs disabled or 3-STATE only.
Conditions
VCC (V) 2.3-2.7 2.3-2.7 2.3-2.7 2.3 2.3 2.3 2.3-2.7 2.3 2.3 2.3-2.7 2.3-2.7 0 2.3-2.7 2.3-2.7
Min 1.6
Max
Units V
0.7 VCC - 0.2 2.0 1.8 1.7 0.2 0.4 0.6 5.0 10 10 20 20
V V V V V V V V A A A A A
DC Electrical Characteristics (1.65V V CC < 2.3V)
Symbol VIH VIL VOH VOL II IOZ IOFF ICC Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current IOH = -100 A IOH = -3 mA IOL = 100 A IOL = 3 mA 0 VI 3.6V 0 VO 3.6V VI = V IH or VIL 0 (VI, VO) 3.6V VI = V CC or GND VCC (VI, VO) 3.6V (Note 9)
Note 9: Outputs disabled or 3-STATE only.
Conditions
VCC (V) 1.65-2.3 1.65-2.3 1.65-2.3 1.65 1.65-2.3 1.65 1.65-2.3 1.65-2.3 0 1.65-2.3 1.65-2.3
Min 0.65 x VCC
Max
Units V
0.35 x V CC VCC - 0.2 1.25 0.2 0.3 5.0 10 10 20 20
V V V V V A A A A A
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74VCX162244
AC Electrical Characteristics (Note 10)
TA = -40C to +85C, CL = 30 pF, RL = 500 Symbol Parameter VCC = 3.3V 0.3V Min tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tOSHL tOSLH Propagation Delay Output Enable Time Output Disable Time Output to Output Skew (Note 11) 0.8 0.8 0.8 Max 3.3 3.8 3.6 0.5 VCC = 2.5V 0.2V Min 1.0 1.0 1.0 Max 3.8 5.1 4.0 0.5 VCC = 1.8V 0.15V Min 1.5 1.5 1.5 Max 7.6 9.8 7.2 0.75 ns ns ns ns Units
Note 10: For CL = 50PF, add approximately 300 ps to the AC maximum specification. Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP Parameter Quiet Output Dynamic Peak VOL Conditions CL = 30 pF, VIH = VCC, VIL = 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 TA = +25C Typical 0.15 0.25 0.35 -0.15 -0.25 -0.35 1.55 2.05 2.65 V V V Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = 1.8, 2.5V or 3.3V, VI = 0V or VCC VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V TA = +25C Typical 6 7 20 pF pF pF Units
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74VCX162244
AC Loading and Waveforms
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6V at VCC = 3.3 0.3V; VCC x 2 at VCC = 2.5 0.2V; 1.8 0.15V GND FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 3.3V 0.3V 1.5V 1.5V VOL +0.3V VOH -0.3V 2.5V 0.2V VCC/2 VCC/2 VOL +0.15V VOH -0.15V 1.8V 0.15V VCC/2 VCC/2 VOL +0.15V VOH -0.15V
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74VCX162244
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A
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74VCX162244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistor in Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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